AMD has lifted the lid on its next-generation EPYC 9006 "Venice" server processors, built around the Zen 6 architecture. The company outlined the lineup at its Advancing AI 2026 event, revealing a top-to-bottom overhaul that includes new sockets, a new I/O die, and a return to 3D stacked L3 cache. The family is expected to be AMD's largest EPYC generation yet, with four major chip variants.
The most striking change is the growing gap between standard and dense chiplets. Both Zen 6 and Zen 6c CCDs are manufactured on TSMC's 2nm process, but dense Venice parts can pack up to 256 cores, compared with 96 for the highest-core-count standard Zen 6 chip. Clock speeds also converge somewhat: standard parts top out at 5.0GHz, while dense parts reach 4.1GHz, 400MHz faster than the previous dense generation.
Memory and I/O get a major boost from a new I/O die. Venice supports up to 16 memory channels, up from 12, with DDR5 RDIMMs running at up to 8000 MT/s and MRDIMM support pushing the bus to 12,800 MT/s. AMD also plans an AI-focused EPYC with LPDDR support arriving in 2027, part of its push to extend EPYC deeper into AI systems alongside the Helios rackscale platform.