AMD's upcoming Epyc 9006 SP7 platform, codenamed Venice, represents the company's biggest CPU architecture shift since Rome in 2019, according to The Register. The lineup splits into two distinct chiplet designs: a density-optimized part with 256 cores and a frequency-optimized part with 96 cores that can boost to 5 GHz. Both use eight core-complex dies (CCDs) around a pair of I/O dies, but the CCDs differ significantly. The density parts pack 32 cores and 128 MB of L3 per chiplet, giving the fully loaded chip a full gigabyte of L3 cache, while the frequency parts use 12-core chiplets with 48 MB of L3.
A notable change this generation is the cache hierarchy: AMD has eliminated the old distinction between Zen 6C and Zen 6 cores. Both compact and standard cores now get at least 4 MB of shared L3 per core, so the only trade-off is core count versus clock speed, not feature set or cache capacity. The Register notes that AMD's compact cores are not like Intel's efficiency cores; they use the same ISA and microarchitecture, just with a more space-efficient layout.
The dual I/O dies keep the same 128 PCIe lanes as previous Epyc parts but double the speed with PCIe 6.0 and add CXL 3.1 support for pooled memory appliances. Memory bandwidth gets a major boost too: 16 channels of DDR5-8000, or 12,800 MT/s with MRDIMMs, yielding a theoretical 1.6 TB/s and roughly 1.3 TB/s in STREAM Triad testing, per AMD. The Register also notes that AMD published a whitepaper aimed at countering Nvidia's claims about its Vera CPUs, though the full performance comparison is still pending.