Designing modern AI and HPC systems means choosing among a rapidly expanding set of compute architectures, memory technologies, and interconnects. GPUs, dataflow processors, RISC-V accelerators, HBM, GDDR, SRAM, NVLink, UALink, InfiniBand, Slingshot, and Ultra Ethernet all compete for consideration. According to researchers at Argonne National Laboratory and the University of Illinois Urbana-Champaign, no single architecture is optimal for every workload, and the resulting combinatorial space is too large for manual exploration.
To address this, the team introduced ArchAgent, a hierarchical multi-agent framework described in an October 2026 arXiv paper. An LLM-based planner decomposes the system design problem into three subproblems—chip, scale-up, and scale-out—and assigns each to a specialist agent. This division lets the framework explore heterogeneous configurations across all three domains in a structured way.
The work is notable for applying agentic AI to hardware design rather than only to software or data-center operations. By automating part of the architectural search process, ArchAgent could help researchers and engineers evaluate trade-offs across compute, memory, and interconnect options more systematically than manual methods allow.