Clock meshes are a standard way to keep clock skew low in high-performance chips, but they eat up premium frontside routing metal. Researchers at UC Santa Cruz have published the first design-space exploration of moving those meshes to the backside of a wafer, where backside power delivery networks already provide thick, low-resistance metal layers that are not fully used by power grids.
The trade-off is that flip-flops remain on the frontside, so a backside mesh cannot drive them directly. Every connection between the mesh and a flip-flop must pass through a through-silicon via, adding resistance and design constraints. The team implemented its exploration in OpenROAD on GT2N, a 2nm nanosheet GAAFET technology, to study how the mesh design space changes under backside power delivery.
The paper, by Wajid Ali, Muhammad Hadir Khan, Dalton Gaddy, and Matthew Guthaus, is available on arXiv. The source reports that the backside approach cuts skew and power, though the abstract excerpt does not include specific numbers. This article is based on a single source, so there are no conflicting findings to compare.