Data center power demand is climbing sharply as AI, high-performance computing, and cloud services push compute density to new levels. The article cites Gartner estimates that worldwide data center power demand will rise 27% in 2026 to 132 GW, up from 104 GW in 2025, and reach 290 GW by 2030. AI-optimized servers are a major driver: they are expected to account for 31% of data center power consumption in 2026 and to surpass conventional servers in power consumption by 2027.
The article argues that power efficiency is no longer just a system-on-chip design problem. Rack-level power limits, facility budgets, and cooling capacity increasingly determine how much compute can be deployed. Conventional frontside power delivery, which routes power and signals through the same metal layers, creates competition for routing resources and adds resistance and inductance as current demands rise. Designers respond with wider power rails, extra decoupling, and larger guard bands, which add cost and complexity with diminishing returns.
Intel Foundry's proposed answer is backside power delivery. PowerVia, introduced with Intel 18A, moves power routing off the signal layers, shortening vertical power paths and reducing IR drop. A second-generation technology called PowerDirect is planned for Intel 14A. The article also highlights capacitor technologies such as Omni MIM, substrate embedded MIM with through-silicon vias, and embedded deep trench capacitors to provide near-load decoupling. These are meant to improve transient response for bursty workloads like AI inference and HPC acceleration.
The piece is authored by Intel Foundry engineers, so the solution focus is on Intel's roadmap rather than a neutral survey of the industry. Still, the underlying problem is clear: as data center power demand grows, the way power is delivered to transistors is becoming a central constraint on system performance and scalability.