As gate-all-around nanosheet transistors approach their practical limit around the A10 node, imec and its partners are preparing complementary FETs (CFETs) for the next stage of logic scaling. By stacking nMOS and pMOS devices vertically, CFETs can reduce standard-cell height from 5.5-track to 3-track, potentially extending the conventional CMOS roadmap to at least the A3 node. Two integration routes are under development: monolithic CFET (mCFET), which processes the stacked structure in one sequence, and sequential CFET (sCFET), which patterns top and bottom devices separately using dedicated masks. The source notes that mCFET is believed to offer the fastest path to industrial adoption, pending progress in alignment accuracy for sCFET's two wafer flips.
Recent work highlights two CFET-specific process modules: a backside contact module and a gate-stack integration approach that enables multiple threshold voltages in nanosheet and CFET devices. These modules are considered essential for both mCFET and sCFET flavors. In parallel, design-technology co-optimization (DTCO) studies propose a scalable sCFET architecture that supports both split-gate and common-gate configurations, which could benefit logic and SRAM scaling. Another DTCO study demonstrates improved back-end-of-line routability to support the scaling of CFET standard cells.
The reported results come from work hosted at imec's European NanoIC pilot line, which targets development of beyond-2nm systems-on-chip. CFET development has been selected as one of the key enabling technologies for extending the logic roadmap into the angstrom era, according to the source.