Semiconductor Engineering gathered experts from Synopsys, Silvaco, Vinci, Keysight EDA, and Siemens EDA to discuss why heat has become a central chip design issue. The panel agreed that advanced designs can no longer treat voltage, timing, resistance, power, and temperature as separate concerns. Synopsys' Lang Lin noted that reducing voltage lowers heat but hurts timing and performance, forcing engineers to run iterative loops of timing, thermal, and power-integrity checks across multiple workloads—yet no tool exists to automate that full loop.
The experts also agreed that vertical scaling, including 3D-ICs, is a matter of when, not if. Silvaco's Jack Berg pointed out that a package with 16 stacked HBMs already qualifies as a 3D-IC by some definitions. But making denser stacks practical will require advances in materials science, hybrid bonding, and cooling, such as interposers with fluid circulation. As Vinci's Satish Radhakrishnan noted, these exotic solutions will be expensive and likely limited to high-performance applications.
A recurring theme was that thermal is a system-level problem, not a single-discipline one. Keysight's Chris Mueth and Siemens' John Ferguson both emphasized the need to integrate heterogeneous technologies and break down silos between materials, thermal, mechanical, and electrical engineering. Ferguson suggested that intelligent MCPs (model context protocols) could help engineers find and build the right cross-disciplinary tools, echoing the panel's broader point: solving heat requires thinking beyond the transistor. The experts differed only in emphasis, not direction—all saw heat as the defining constraint for the next era of chip design.{