The latest chip-industry paper roundup from Semiconductor Engineering includes new research on several fronts. A group from KAIST, TDS Innovation, Hanyang University, and UNIST describes a method for spatially deterministic nucleation of 2D semiconductors by etching flux. Separately, researchers from UIUC, Argonne, and Monash propose using a carbon-dot monolayer as a van der Waals interfacial layer to integrate high-κ oxides on 2D semiconductors.
In AI hardware security, a team from University of Florida, UT Dallas, and RPI presents BARE-AI, a system that uses built-in performance monitors to detect bit-flip attacks. On the memory side, ETH Zürich, CISPA, and NYU propose Terracotta, a flexible DRAM interface and memory controller designed to ease adoption of new DRAM techniques. Also, Carl Zeiss SMT and ASML describe Hyper-NA, a system with a numerical aperture of at least 0.75.
Additional papers cover monolithic 3D integrated memristor-thin-film transistors for reservoir computing (Seoul National University, Yonsei) and low-loss ultra-compact photonic bends with enhanced fabrication tolerance (Georgia Tech). The papers come from different groups and do not share a single theme, but together they reflect ongoing work across materials, architecture, and security in chip design.