The latest technical paper roundup from Semiconductor Engineering spans a wide range of topics, from AI-driven design tools to memory and thermal modeling. One entry, from Argonne National Laboratory and the University of Illinois Urbana-Champaign, proposes using agentic AI for heterogeneous system design, covering chip, scale-up, and scale-out domains.
Another paper, from Sandia National Laboratories and the Luxembourg Institute of Science and Technology, uses predictive first-principles simulations to reveal new leakage paths in gate-all-around FETs (GAAFETs). Separately, a collaboration between UC Berkeley, Samsung Electronics, and Intel describes a nanoelectromechanically gated gain cell eDRAM, which could offer a new approach to dense embedded memory.
The roundup also includes work from Cadence and the University of Notre Dame on a composable AI-accelerated iterative solver for 3D-IC thermal modeling, and an experimental study from ETH Zürich and New York University analyzing power consumption in real HBM2 DRAM chips. A paper from Columbia University and Google explores rethinking EDA infrastructure for agentic systems in chip design verification, while Missouri University of Science and Technology surveys thermal side-channel and perception attacks on autonomous vehicles.
Because this is a single roundup source, there are no conflicting findings to reconcile; the papers are presented as separate contributions to the field.