The latest chip research roundup from Semiconductor Engineering highlights a wide range of topics, from future transistor architectures to hardware security. One paper compares A7 CFET and A10 nanosheet FET technologies, examining cell parasitics and chip reliability. Another demonstrates wafer-scale 2D MoS2 transistors with sub-5nm channel lengths, claiming subthreshold performance beyond the silicon limit.
Additional papers explore power delivery for advanced 3D heterogeneous integration, the impact of copper microstructure on through-silicon via residual stress, and methods to amplify Rowhammer attacks on ECC-protected GPUs. Other research covers gate-level localization of RTL trojans, concurrent host memory and HBM access for LLM inference, and whether agents can design chips at a higher abstraction level.
Together, these papers reflect ongoing efforts across academia and industry to push compute performance, improve reliability, and address emerging security threats in hardware.