Semiconductor Engineering's Oct. 6 roundup adds six papers to its library, spanning device physics, chip design, memory, and security. Researchers from HUST, PolyU, UC Santa Barbara, and NUS report that oxygen-doped WSe2 monolayers can achieve low contact resistance and high current density in ballistic p-type transistors, a possible step for 2D material logic.
At the design level, UC Santa Cruz examines backside clock meshes for 2nm GAAFET technology with buried power distribution networks. Separate work from Syracuse, FAU Erlangen-Nürnberg, and TU Dresden proposes RAPID, a row-parallel arithmetic processing scheme in DRAM. UC Berkeley and FuriosaAI characterize high-bandwidth flash for LLM serving, while Georgia Tech, Qatar Computing Research Institute, and Purdue provide a formal security analysis of CAN XL.
Infineon and TU Munich contribute a paper on abstraction and validation in hardware engineering, covering the move from physical devices to RTL models. Since the source is a single roundup, there are no conflicting findings to compare; the entries are presented as newly added research.