The latest Semiconductor Engineering blog review spans several distinct hardware topics, from transistor-level design to chiplet interconnects and AI inference performance. The items are not part of a single narrative; they reflect the breadth of current engineering work.
On the compute side, Siemens' Karen Chow, Sheetal Veronica, and Kunjesh Agashiwala describe how CFETs and buried power rails can shrink chip area and improve power efficiency for AI accelerators, data centers, and mobile processors. Arm's Francisco Socal introduces AMBA C2C, a chiplet connectivity extension that works across AXI and CHI with scalable protocol subsets and flexible transport support for coherent heterogeneous compute. Separately, Imagination's Alex Pim examines time to first token and inter-token latency in the prefill and decode stages of LLM inference.
Other posts cover agentic AI in EDA, 6G prototyping, roots of trust, PCIe-over-UCIe integration, and sustainable semiconductor startups. Because this is a roundup, the posts are independent; no source disagrees with another, but they also do not converge on a single conclusion.