Thermal analysis for heterogeneous 2.5D/3D-IC packages is a bottleneck: a full-package finite-element simulation can take hours, and existing AI-based surrogates treat the entire stack as one fixed structure, forcing retraining whenever the die count or layout changes. In a new paper, researchers from Cadence Design Systems and the University of Notre Dame propose DAIST, a composable solver that decomposes the global package into block-level subdomain problems and replaces the subdomain solvers with neural operators.
The subdomains are coupled through iterative exchanges of interfacial temperature and heat flux, creating a local-to-global architecture that avoids the topology lock-in of monolithic models. Because each block-level neural operator is trained independently, it can be reused in structurally different package assemblies without retraining. The iterative coupling also gives users a tunable accuracy-runtime tradeoff: adjusting the iteration budget can exchange accuracy for speed.
Evaluated on a multi-chiplet system and an advanced packaging system, DAIST achieved up to 178x speedup over traditional FEM solvers, with mean temperature errors of 0.068% and 0.323% respectively. The paper also demonstrates cross-topology reuse of block-level models across distinct package assemblies, a key step toward making AI-accelerated thermal analysis practical for rapidly changing chip designs.
This is a single research report, so there are no conflicting sources to compare. The main caveat is that the results come from the authors' own test cases, and broader adoption would require validation on a wider range of packaging configurations and integration into commercial design flows.