As through-silicon vias (TSVs) shrink, the mechanical stress they impose on surrounding silicon becomes a bigger reliability concern. A new paper from Purdue and UCLA provides direct experimental evidence that the copper grain structure inside a TSV significantly influences that stress—not just the via's size or pitch.
The team fabricated a 3-micrometer-diameter TSV array, annealed it at 400°C for 60 minutes, and mapped residual stress in the silicon using Raman spectroscopy at room temperature. They paired that with electron backscatter diffraction (EBSD) to characterize the copper's surface microstructure, allowing them to deduce a microstructure-dependent effective elastic modulus.
The results show that copper grains with different orientations and sizes respond differently to thermal cycling, leading to non-uniform stress fields in the silicon. This means that two TSVs with identical dimensions can produce different stress profiles if their copper microstructures differ—a factor often ignored in standard design rules.
The authors, S. Lyu, T. Beechem, and T. Wei, published their findings in Advanced Electronic Materials (2026). The work suggests that controlling copper deposition and annealing conditions to tune grain structure could become a practical lever for managing stress in advanced 3D integrations, complementing geometric design changes.