The semiconductor industry's shift to chiplet-based designs is colliding with the rise of physical AI systems such as autonomous vehicles, robots, and drones. These systems generate continuous streams of sensor data, feature maps, and inference results that must move between specialized accelerators. The article argues that today's coherent die-to-die interconnect protocols, designed for cache-line-sized memory transactions, are a poor fit for these large, deterministic data flows.
Existing non-coherent alternatives, including AXI Chip2Chip and AXI over UCIe, still force NoC packets to be converted into AXI transactions at each die boundary, adding latency and buffering. The proposed alternative is to let the network-on-chip span multiple dies directly, carrying native NoC packets across the interface. This makes the die boundary just another hop in a single logical network, allowing routing, arbitration, congestion management, and quality-of-service mechanisms to extend across chiplets.
According to the source, this direct NoC-to-NoC approach amortizes protocol overhead across long streams, supports multiple traffic classes through virtual channels, and can carry AXI, APB, AHB, or OCP over the same physical link. For automotive physical AI, where latency, determinism, and power are critical, the article says this architecture is a more natural fit than repeatedly translating between NoC packets and cache-line transactions.