For years, AI and HPC chip design has focused on compute throughput, but a white paper from Synopsys, highlighted by Semiconductor Engineering, argues that embedded memory is now the real bottleneck. It consumes more than half of total die area in these SoCs and directly limits bandwidth, latency, and energy efficiency.
The paper says the transition to gate-all-around (GAA) devices and backside power delivery networks (BSPDN) reshapes what embedded memory IP must deliver. To keep pace, designers need device-aware architectures, power-optimized designs, and highly configurable compilers that can adapt memory to the new transistor and power-delivery environment.
Silicon results from SRAM and register file test chips on Intel 18A show density improvements in the 5–10% range and iso-power performance gains of up to roughly 4%. The paper attributes these gains to RibbonFET and PowerVia, and says they enable measurable PPA improvements while reducing advanced-node integration risk.