Photonic integrated circuit (PIC) performance is increasingly constrained by real fabrication effects—sidewall angle, critical-dimension bias, thickness variation, and line-edge roughness—that conventional as-drawn FDTD simulations fail to capture. A recent article in Semiconductor Engineering describes a Fab Technology Co-Optimization (FTCO) workflow that directly addresses this gap by integrating GDS layout import, three-dimensional process simulation, GPU-accelerated FDTD, design of experiments (DOE), and AI-based surrogate modeling.
When manufacturing variations are included, the simulation results align closely with experimentally reported results, according to the article. The workflow was demonstrated on a directional-coupler DOE with 25 unique combinations of four process variations, requiring a 65-million-cell 3D FDTD model that completed in under 10 hours on a single NVIDIA A100-equipped workstation.
The resulting digital twin gives non-simulation experts intuitive, real-time access to the process-to-performance relationship. This approach could make manufacturing-aware simulation practical for routine PIC design, rather than a specialized post-layout check.