Researchers from ETH Zürich and New York University have published the first detailed experimental characterization of power consumption in real HBM2 DRAM chips. The study, based on measurements of actual chips rather than simulations, provides an empirical foundation for building or validating HBM power models. It also highlights how much power varies with both memory structure and the data being accessed.
Two findings stand out. First, read operations draw significantly more current than any other operation, making them the dominant power event in normal use. Second, the state of the data bus during a burst matters: toggling all HBM2-internal bank group bus signals increases power consumption by 29.4% compared to keeping them constant. This means that seemingly minor details in access patterns can have a large effect on energy use.
Using these insights, the team engineered an access pattern that, on average across 36 tested HBM2 chips, consumed 23.6% more power than the highest-power JEDEC-specified current measurement loop. That result suggests existing industry test patterns may underestimate worst-case power, which is relevant for system designers who need to budget for thermal and electrical limits. The paper is available as an arXiv preprint from October 2026.