Humanoid robots are beginning to move out of research labs and into warehouses and factories, and that shift is putting new stress on the memory chips embedded throughout their bodies. A Semiconductor Engineering analysis notes that shipments could rise from fewer than 15,000 units in 2025 to more than 6 million by 2035, according to Goldman Sachs. The architecture resembles a zonal design: a central compute core handles AI and vision, while distributed microcontrollers manage motors, joints, and battery systems. Each tier needs a different kind of memory.
At the edge, the requirements are especially demanding. Standard NOR flash and EEPROM devices take 5 to 10 milliseconds to write a page, and if power is lost mid-write, a robot can lose its absolute joint coordinates and need a disruptive homing sequence. Heat is another problem: compact joints can exceed 100 degrees Celsius, which accelerates charge leakage in conventional charge-based memories and shortens data retention. Electromagnetic interference from high-torque motors can also flip bits in telemetry logs. The source says ferroelectric RAM, or F-RAM, offers zero write-cycle delay, roughly 100 trillion write cycles, and native immunity to magnetic fields, making it a candidate for joint and battery controllers.
Centralized AI workloads, by contrast, still rely on high-bandwidth DRAM and NAND flash for model execution and storage, while functional-safety NOR flash with on-chip error correction is used on AI accelerator boards. The article stresses that there is no single accepted memory architecture for humanoid robots; instead, designers are selecting different memory types for each subsystem based on whether they prioritize bandwidth, latency, endurance, or power-loss resilience.