According to Tom's Hardware's analysis of Intel's packaging roadmap, EMIB and Foveros are becoming more sophisticated and more complementary. EMIB began as a way to connect adjacent chiplets without a full silicon interposer, embedding small silicon bridges in an organic substrate only where dense die-to-die links are needed. The roadmap shows the first-layer interconnect bump pitch dropping from 55µm in first-gen EMIB to 45µm today, with further reductions to around 36µm and ultimately 25µm or below, increasing the number of connections along chiplet edges.
Intel is also adding functionality to the bridges themselves. EMIB-M integrates metal-insulator-metal capacitors to smooth power delivery near compute dies, while EMIB-T adds through-silicon vias so power can travel vertically through the bridge. These changes matter for multi-kilowatt system-in-packages and HBM4-class memory, where current density and power integrity are major constraints. The source notes that EMIB and Foveros are no longer separate approaches; they complement each other and Intel's process technologies, with the ultimate goal of building 12-reticle system-in-packages using both EMIB and Foveros Direct 3D.
On the package-size front, Intel has moved from 4X reticle SiPs on 80x80mm packages to roughly 8X reticles on 120x120mm packages today, and plans 12X SiPs on 120x180mm packages. Future EMIB-T evolutions may combine finer-pitch bridges with glass-core substrates, enabling even larger panels. The analysis frames these changes as a way to scale chips in both 2.5D and 3D without relying on a single monolithic die.