According to a Semiconductor Engineering analysis, the same compute advances that made large language models possible have also triggered a wave of custom silicon development. Major AI companies are increasingly designing their own chips, but building an ASIC remains a huge undertaking: more than 1,000 engineering months for a typical chip, along with scarce specialized talent and significant capital risk.
Most of that effort now goes into functional verification. The article says verification accounts for 60–70% of chip development effort, spanning block-level, subsystem-level, and full-chip checks across simulation, formal methods, and emulation. That marks a shift from earlier decades, when synthesis and place-and-route were the main bottlenecks. EDA tools and hardware description languages such as Verilog automated those later stages, leaving verification as the most human-intensive part of the flow.
The article's headline argument is that LLMs are the best thing to happen to chip design because they target exactly this problem. It does not lay out a detailed technical roadmap, but it frames LLMs as a potential productivity lever for the most expensive and reasoning-heavy stage of chip development.