Microsoft has released feeds and speeds for its next homegrown accelerator, the "Clea" Maia 300, timed to the start of the Open Compute Project Summit 2026. The company describes it as a system in a socket rather than a strict system on a chip: seven chips and eight HBM stacks on an interposer. The design is tuned for real-world GenAI inference, not for stacking up floating-point numbers on a spec sheet.
The target workload is agentic — dozens to hundreds of models working together, whether as a mixture-of-experts foundation model, physically separate models, or a blend of the two — all needing to share the same network and memory space at low latency. To that end, Microsoft changed its AI Transport Layer RoCE Ethernet implementation so more XPUs fit in a rack and more racks fit inside a single coherent domain.
Maia 300 follows the Athena Maia 100, introduced in November 2023, and the Braga Maia 200, unveiled in January 2026 and now ramping into Azure production. Scott Guthrie, Microsoft's executive vice president for Cloud and AI, called the multigenerational Maia program "a foundational element of Microsoft's AI infrastructure strategy," saying Maia 200s are running Copilot inference and that GitHub Copilot and Microsoft Foundry will shift onto them by the end of the year. The Maia 200 brought 2.3X more ATL bandwidth, a 2.7X larger coherence domain at 6,144 devices for only 1.5X the power, a move from 6-bit MX6 to 4-bit MXFP4 data formats, 1.5X more compute cores, and 3.4X the floating-point throughput of Athena.
On scale, the report cites a rumour that Microsoft wants at least 1 million Maia sockets deployed, alongside Guthrie's statement about multi-gigawatt Azure deployments. By the article's arithmetic, a gigawatt of Maia 300s works out to roughly 575,000 devices at 1.74 kilowatts each, counting the accelerator plus its share of host, storage and scale-up networking; a rack is about 167 kilowatts across 96 interlinked XPUs. Two caveats: this is a single source, and the available text is truncated mid-sentence in its discussion of the Braga tile layout, so the bandwidth specifics implied by the headline are not detailed here.