As SRAM scaling slows and the memory wall persists, researchers are looking again at gain-cell embedded DRAM as a denser, more energy-efficient alternative. But gain cells have known drawbacks: short data retention, unwanted coupling between nodes, and the need for boosted voltages during writes. A new paper from UC Berkeley, Samsung, and Intel proposes a way around these limits by swapping the transistor gate for a nanoelectromechanical (NEM) switch.
The idea is to use a mechanically actuated, nanoscale switch as the gate of the gain cell. Because NEM switches can achieve a very abrupt on/off transition with extremely low leakage in the off state, they could hold charge longer and reduce the parasitic coupling that plagues conventional gain cells. The authors report that this approach also removes the need for boosted write voltages, which would simplify the peripheral circuitry and improve overall energy efficiency.
The paper, "Nanoelectromechanically Gated Gain Cell eDRAM," appears in the IEEE Journal on Exploratory Solid-State Computational Devices and Circuits. The authors include researchers from UC Berkeley, Samsung Electronics, and Intel. The work is at an exploratory stage, but it points toward a possible path for embedded memory that is both denser and more power-efficient than today's SRAM-based caches.