A new technical paper from TU Munich, the University of Modena and Reggio Emilia, and Applied Materials presents a physics-based, thermal- and aging-aware system-technology co-evaluation (STCO) flow for comparing A7 CFET and A10 nanosheet FET (NSFET) technology nodes. The flow links calibrated device models, optimized standard-cell generation, automated GDS-to-TCAD conversion, accurate 3D parasitic RC extraction, full RTL-to-GDS implementation of an AI accelerator, multiphysics thermal analysis, and physics-based bias temperature instability (BTI) aging evaluation.
By using the same device model for both technologies, the researchers say they can isolate the impact of parasitic RCs and design decisions at different levels of the design flow. This allows them to assess how each architecture behaves from cell parasitics up to full-chip reliability, rather than attributing differences solely to the transistor structure itself.
The paper, published on arXiv in September 2026, is titled "System-Technology Co-Evaluation of A7 CFET and A10 NSFET Technologies from Cell Parasitics to Chip Reliability." It represents a step toward earlier evaluation of competing transistor designs in the context of real workloads and reliability constraints, particularly for AI accelerator chips where thermal and aging effects are critical. The source does not report specific performance or reliability results, only the methodology and its intended purpose.