Nvidia's Vera server chip leans on a second-generation Scalable Coherency Fabric (SCF) to feed its Olympus cores. The SCF is a chip-wide network built from several node types: Coherency Switch Nodes host pairs of cores and cache, Memory Switch Nodes bridge to the memory controllers, and Bridge Switch Nodes handle PCIe and the cross-socket link. This mesh-like design keeps node count manageable while supporting high core counts.
The memory subsystem is a major departure from Grace. Vera uses a 1024-bit LPDDR5X-9600 setup capable of up to 1.228 TB/s of bandwidth, and latency is now comparable to DDR5-based servers. Unlike Grace's soldered memory, Vera adopts SOCAMM2 modules, making memory field serviceable and potentially upgradeable. Under heavy bandwidth load, a pointer-chasing thread still stays under 200 ns of latency, avoiding the sharp latency cliff seen on other platforms.
Vera also brings a 164 MB shared L3 cache with a non-inclusive relationship to core-private L2 caches, yielding up to 340 MB of effective last-level capacity when there's no duplication. L3 read bandwidth is about 3.35 TB/s total, or 33.1 GB/s per core with contention, while a single core can reach 88.5 GB/s alone. This contrasts with AMD's approach, which emphasizes high per-instance bandwidth and large aggregate capacity but can duplicate shared data across clusters.
For dual-socket scaling, NVLink C2C provides a point-to-point link with reads exceeding 587 GB/s and a read-modify-write pattern reaching 780 GB/s. Cross-socket load-to-use latency is 309.27 ns, but only after generating a few dozen GB/s of traffic; an isolated pointer chase sees over 370 ns. This suggests the link enters a higher-performance state only when bandwidth demand is sufficient, a quirk worth noting for latency-sensitive workloads.