Semiconductor Engineering reports on a push to predict silicon behavior long before test wafers are produced. The approach centers on wafer-validated optical simulation for high-NA EUV applications, letting engineers model lithography outcomes earlier in the development cycle.
Because high-NA EUV tools and processes are still maturing, relying solely on physical test wafers can slow learning and raise costs. Simulation offers a way to explore patterning behavior in advance, with validation against real wafers used to keep the models credible.
The source does not claim simulation replaces wafer testing entirely. Instead, it frames the technique as a way to gain foresight into silicon behavior years ahead, complementing physical experimentation as high-NA EUV moves toward production.