AI data center power design has moved beyond rack-level architecture questions to the control layer, according to Semiconductor Engineering. The challenge is no longer just moving enough power into dense racks; it is doing so while switching faster, regulating faster, and protecting faster without making firmware unmanageable. Wide-bandgap devices such as GaN and SiC push switching frequencies higher, and AI workloads demand faster dynamic response from every conversion stage.
Infineon's PSOC Control C3 Performance Line MCUs are positioned as the silicon-level answer. The devices include a Programmable Power Control Accelerator, a 25 MSPS ADC subsystem, sub-100 ps high-resolution PWM, comparators with slope generation, and hardware 3P3Z filters. Custom logic, an event processing unit, PMBus and CAN FD interfaces, plus safety and security features round out the part. The idea is to give designers hardware that can handle timing, sensing, and compute in one place.
According to the source, the MCUs target three main applications: power supply units running interleaved power-factor correction and LLC stages, intermediate bus converters regulating a 48 V or high-voltage bus close to the load, and battery backup units that must transition among charge, discharge, ORing, and protection states. The source does not compare these MCUs with competing parts; it focuses on mapping system-level pain points to specific on-chip features.