Researchers from Syracuse University, Friedrich-Alexander-Universität Erlangen-Nürnberg, and TU Dresden have proposed RAPID, a row-parallel arithmetic processing-in-DRAM architecture. Processing-using-memory systems reduce costly data movement by computing inside DRAM, but existing designs rely on charge-sharing operations confined to individual bitlines. That forces data into column-oriented, bit-serial representations, which are fundamentally different from the row-oriented, word-parallel layouts used by conventional processors and accelerators. As a result, data must undergo expensive layout transformations whenever computation moves between PUM and normal execution.
RAPID addresses this by augmenting each DRAM subarray with two lightweight extensions: migration cells, which enable localized horizontal data movement between neighboring bitlines, and inversion cells, which provide efficient in-array logical inversion. These primitives allow RAPID to operate directly on row-parallel, bit-parallel data, preserving CPU-compatible layouts while taking advantage of the DRAM subarray's parallelism.
The work is described in an arXiv preprint released in October 2026. Since only this source was available, there are no conflicting findings to compare; the paper reports the architecture and its claimed benefits without independent validation in the source material.