Gate-all-around field-effect transistors (GAAFETs) are expected to replace FinFETs at advanced semiconductor nodes because of their superior electrostatic control. Yet recent measurements have shown that GAAFET drain current deviates strongly from thermionic behavior at negative gate voltages, with leakage increasing as the gate voltage becomes more negative. That anomaly had not been fully explained.
A team from Sandia National Laboratories and the Luxembourg Institute of Science and Technology set out to trace the mechanism. Using predictive, charge-self-consistent Non-Equilibrium Green Function (NEGF) simulations based on the Contact Block Reduction (CBR) method, they spatially resolved the leakage pathway in a single-sheet GAAFET device. Their results attribute the leakage to direct gate-drain tunneling through the high-k dielectric, an effect made worse by drain-induced dielectric barrier lowering (DIDBL).
The findings, published as an arXiv preprint in October 2026, provide a concrete physical picture of a failure mode that could affect the reliability and power consumption of future GAAFET-based chips. By identifying exactly where and how charge escapes, the work gives device designers a clearer target for mitigation strategies, such as adjusting the dielectric stack or modifying the drain region. The paper is available under a Creative Commons license.