SK hynix has detailed plans to put custom-designed tiny cores, called H-TPU, into its SSD controllers. The cores are meant to take over repetitive storage tasks from the main Arm CPU, which the company says is reaching power and area limits as PCIe bandwidth doubles each generation. According to a talk by SK hynix VP Koo In-jae at ISOCC 2026, each H-TPU draws only about 2.5% of a general-purpose core's power and takes up roughly 4% of its area.
The H-TPU is a small, programmable core with a four-stage in-order pipeline, not an AI accelerator. Clusters of these cores handle read/write command processing, metadata management, and buffer control, while the main CPU keeps responsibility for error recovery, exception handling, and storage-policy management. SK hynix says the design can idle cores that a given I/O operation does not need, dropping them into a minimum-power mode.
The approach resembles Phison's CoXProcessor, which uses small Cortex-R5 cores to offload repetitive firmware work, but SK hynix is scaling it up to more than 100 H-TPUs. The company also described a next step called hardware automation (HWA), moving some routine jobs into fixed circuits to keep completion times predictable. The report notes that the talk was light on architectural details, with SK hynix patents filling in some of the picture, including a pipeline that passes commands through groups of small processors in order.