Co-packaged optics promise to replace electrical interconnects with optical engines attached directly to the package substrate, enabling full-duplex speeds above 100 Tbps from an XPU package. But that performance comes with a thermal problem: the advanced multi-chip package described by Ayar Labs and Global Unichip Corp. (GUC) houses 2 XPUs, 8 HBM4 memory modules, 4 I/O chiplets, and 8 TeraPHY optical engines in a 105mm x 140mm footprint, drawing more than 3 kW of power.
To test whether such a design can stay within operating temperatures, the two companies ran thermal co-simulations that combined electrical behavior and heat flow across the package. The results were mixed. A standard air fin heatsink at 5-6 m/s airflow significantly exceeded temperature specifications for every component except the I/O die. An impingement-type cold plate at 4.5 LPM, however, met spec for all components.
The cold plate worked because it achieved the thermal resistance targets identified in the simulation: no more than 0.008 K/W for the ASIC and 0.15 K/W for the optical engine. The authors say the co-simulation data show CPO can operate reliably within the thermal envelope of advanced multi-chip packages, and they are sharing the results to give hyperscalers confidence in CPO deployments. The study deliberately stressed the system to probe hotspots and thermal crosstalk, rather than avoiding the hard questions.