The paper introduces CHERI-D, an architectural extension to CHERI, a capability-based hardware security model. The extension is designed to support efficient temporal memory safety, which addresses the safe reuse of memory after it has been freed.
The authors note that efficient memory safety is an increasing priority for programming languages, operating systems, and hardware designs. This context suggests CHERI-D is motivated by the need to integrate temporal safety mechanisms more directly into the architecture.
The abstract provides only a high-level description, with no details on implementation, performance, or evaluation. As a result, the specific mechanisms and trade-offs of CHERI-D are not yet available from this source.