Multiple patterning lithography (MPL) has been a key technique for improving resolution in advanced semiconductor nodes, but its cost escalates as feature sizes shrink. Directed self-assembly (DSA) has emerged as a cost-effective complement, though integrating it with MPL requires careful layout decomposition.
The new arXiv paper introduces a graph neural network (GNN)-guided local refinement strategy for layout decomposition in DSA-MP. The approach aims to improve efficiency by focusing refinement on local regions rather than global optimization.
While the abstract does not provide quantitative results, the method addresses a practical bottleneck in advanced lithography. The combination of GNNs with DSA-MP suggests a data-driven path to reducing computational overhead in mask design.