Firmware developers rely on printf-style logging to debug full-chip SoC designs, but in cycle-accurate RTL simulation that convenience comes at a steep cost. Formatting even a short 30-character message with a single argument inside the simulated environment consumes significant simulation cycles, slowing verification runs.
The paper "Stop Paying by the Letter" proposes a host-side tokenized logging scheme. Instead of formatting each message on the simulated target, the design emits compact tokens that the host-side simulator expands into full text. This shifts the expensive formatting work off the critical simulation path.
The authors argue this reduces the logging tax while retaining the diagnostic detail engineers need. The approach is aimed at full-chip verification, where printf overhead can otherwise dominate runtime and delay design closure.