Design-rule checking (DRC) is a critical but time-consuming step in chip layout, where violations must be fixed without altering the circuit's intended function. Researchers at Purdue University have developed DRC-Aid, an agentic framework that automates this local repair process. The system uses large language models at inference time to reason about violations and generate fixes, closing the loop between detection and correction.
The framework is described in a technical paper titled "DRC-Aid: Design-Rule Correction via Agentic Framework utilizing Inference-Time Large Language Models." According to the abstract, DRC-Aid operates as a closed-loop system that targets local DRC repairs. A key feature is that it preserves layout equivalence—meaning the repaired layout maintains the same electrical behavior as the original, which is essential for ensuring the chip still works as designed.
This work addresses a bottleneck in chip design: manual DRC fixing is error-prone and scales poorly as designs grow. By automating local repairs with an agentic AI approach, DRC-Aid could reduce design iteration time and free engineers to focus on higher-level tasks. The paper's details suggest the method is particularly suited for incremental corrections rather than global layout changes, a distinction that matters for practical adoption in existing design flows.