Researchers at Peking University have published a technical paper describing a new approach to predicting thermal conductivity in advanced chip interconnect stacks. The work focuses on the back-end-of-line (BEOL) portion of a chip, where metal wires and dielectrics carry signals between transistors, and where heat buildup has become a growing concern at smaller technology nodes.
The proposed framework connects structural information to thermal conductivity values, and is built on data from extensive layer-resolved thermal measurements. Rather than relying on bulk assumptions, the model accounts for how individual layers within the interconnect stack conduct heat differently.
The paper, titled “Predictive Structure to Thermal Conductivity Modeling Framework for BEOL Interconnect Stacks in Advanced Technology Nodes Enabled by Extensive Layer Resolved Thermal Measurements,” was covered by Semiconductor Engineering. No other sources were available for this report, so the findings are presented as described in that coverage.