A collaboration of researchers from Carnegie Mellon University, the University of Florida, MIT, and Texas A&M University has published a technical paper detailing wafer-scale fabrication of monolayer molybdenum disulfide (MoS2) transistors with channel lengths below 5 nanometers. The work, reported by Semiconductor Engineering, demonstrates that 2D materials can be integrated at scale while maintaining aggressive scaling.
The team's transistors show subthreshold performance that goes beyond the silicon limit, meaning they can switch more efficiently at these tiny dimensions than conventional silicon devices. This is significant because silicon transistors face fundamental physical barriers as they shrink below roughly 5 nanometers, including short-channel effects that degrade performance.
By using a single layer of MoS2—a transition metal dichalcogenide—the researchers achieved better electrostatic control over the channel. The wafer-scale aspect is crucial: it moves 2D transistors from lab curiosities toward manufacturable technology. The paper's abstract highlights that the devices achieve subthreshold swing and other metrics that surpass silicon's theoretical capabilities.
While the source does not mention specific performance numbers or yield statistics, the claim of wafer-scale fabrication with sub-5nm channels is a notable step. The next challenges will likely involve integrating these devices into existing fabrication processes and ensuring uniformity across wafers, but this work provides a strong foundation for post-silicon computing.